��������

This event continues to grow every year as wafer-level packaging gains traction in the semiconductor industry. The overall attendance of 720 technologists from 19 countries in 2014 grew nearly 26% more attendees than the 2013 event.

This paper presents Invensas' silicon interposer technology for heterogeneous chip integration. Various process module and integrated blocks were optimized for yield and high performance in the interposer. The modules under evaluation include TSV etch, barrier deposition, electrochemical plating, chemical mechanical polishing (CMP), temporary bonding, low temperature oxide (LTO) and low temperature polyimide (LTPI) passivation.

Bond Via Array (BVA) technology has been developed to enable more than 1000 vertical connections between memory and processor components in a standard outline Package-on-Package (PoP) configuration. This higher density interconnect more than doubles current PoP capability and thereby addresses next generation wide IO mobile device demands for increased bandwidth [1]-[3].

For 2.5D and 3D IC packaging, wafer back side processing often has temperature limits substantially lower than curing temperature of conventional polyimide (PI). New low temperature curable insulation materials possess very different properties and require thorough evaluation to ensure process compatibility and product reliability.

We compare the influence of different assembly sequences, process parameters and material properties on the resulting package and interposer warpage in 3D stacking configurations.

Computing platforms are trending towards multi-core and low power processors coupled with high bandwidth memory in close proximity for both client and cloud applications. The most critical feature to keep increasing the performance is the processor-memory interconnect.

Multi-Core Processors: Significantly increased the need for multiple memory channels, channel bandwidth and total memory

One of the key enablers for the successful integration of 3-D interconnects using the Through-Silicon Via (TSV) schemes is the control of the mechanical stresses in the Cu TSV itself as well as in the surrounding silicon substrate.

Bond-Via-Array (BVA™) technology has been developed to address the high density interconnect requirements of the next generation of package-on-package (PoP) solutions.

Improved electrical and thermal performance due to shorter electrical paths between the die and the substrate. Better power ground distribution. High packaging density and scalability

This paper describes the utilization of non-destructive imaging using 3D x-ray microscopy for package development and failure analysis. Four case studies are discussed to explain our methodology and its impact on our advanced packaging development effort.

The μPILR interconnect is a copper pillar manufactured as a part of a substrate pad. In this paper, we discuss the electromigration (EM) performance of Pb-free μPILR interconnects in a multi-pair daisy chain within 150μm pitch flip-chip packages.